During integrated circuit manufacturing, photoresist patterns are formed on conductive or dielectric layers on a semiconductor wafer. After the patterns are formed a plasma or wet etch may be performed to transfer the photoresist pattern into the conductive or dielectric layers forming geometric structures such as interconnect leads or contact holes. When a new photoresist pattern is formed on the wafer it must be aligned to the geometries already existing on the wafer.
Alignment marks are used to align photoresist patterns with semiconductor wafers prior to performing deposition, to ensure the resulting features are aligned with prior features already present on the wafer. Alignment marks formed using LOCOS oxide features have sloped sidewalls, which can make alignment difficult or impossible as the alignment mark is not sufficiently sharp for machine vision tools to identify and align to.
Modern photolithography tools require the angle of the sidewalls on alignment mark trenches to be greater than about 70 degrees to avoid alignment errors. Alignment errors may occur when modern photolithography tools attempt to align to the sloped sidewalls formed by LOCOS. Improvements are therefore needed.